Computer systems and other electronic systems rely on the communication of digital data. Synchronous Dynamic Random Access Memory (SDRAM) devices are commonly used in computer systems and such SDRAM devices cooperate with processor devices to support data read and write operations. The Joint Electron Device Engineering Council (JEDEC) publishes specifications related to double data rate (DDR) SDRAM devices.
JEDEC created a standard for the Stub Series Terminated Logic (SSTL) drivers in order to provide a termination mechanism for high-speed signaling applications such as DDR-SDRAM memories. Although both the memory operation frequencies and the requirements for faster memory interfaces continue to increase, the STTL standard is still widely accepted. Current memory systems are predominantly based on the DDR3 and DDR2 standard.
An SSTL driver for DDR2 memories includes an input driver, an output driver and a termination driver. It supports a maximum frequency of 533 MHz and operates under supply voltage of 1.8V. The output driver has an output impedance of 18 Ohm and the termination driver presents impedance of 50 Ohm, 75 Ohm, 150 Ohm and when interruptible it achieves infinite resistance. On the other hand, the SSTL driver for DDR3 memories consists of an input driver and the merged output driver/termination driver. It supports a maximum frequency speed of 800 MHz and operates under a supply voltage of 1.5V. The output driver has an output impedance of 34 Ohm and the termination driver achieves impedances of 120 Ohm, 60 Ohm, 40 Ohm, 30 Ohm and 20 Ohm.
Thus the same driver cannot support both standards (DDR2 and DDR3), nor can operate under different supplies. Typically different drivers are used to support DDR2 and DDR3 systems.
Thus, it is desirable and advantageous to have one driver for allowing a computer processor to interface with both DDR2 and DDR3 systems.